As is known, discrete power semiconductor devices used in a space environment, for example, in space systems such as orbital satellites or vehicles for space exploration, typically must intrinsically have a high reliability. In particular, these devices must be resistant to space ionizing radiation, such as electromagnetic radiation of extremely high energy and penetrative power (gamma rays), beams of protons or electrons with energies even much higher than one MeV, cosmic rays constituted by more or less heavy ions having energies even higher than one TeV, or secondary irradiation by electromagnetic beams or beams of particles generated within the same space systems due to interactions with the cosmic radiation. The interaction between the above sources of radiation or particles and the semiconductor device during operation can trigger mechanisms of electrical degradation (ionization) or physical degradation (lattice dislocation), which can evolve in a quasi-instantaneous or cumulative way up to thermal destruction of the device.
In discrete power MOSFET devices, the mechanisms underlying the possible physical degradation or failure are basically of two types, known as:                TID (Total Ionizing Dose), i.e., generation of electron-hole pairs within dielectric layers and consequent accumulation, over time, of trapped charge, prevalently holes, in active and passive layers of the device, with progressive degradation of its operating characteristics;        SEE (Single-Event Effects), i.e., quasi-instantaneous triggering of mechanisms of localized energy overload, which can give rise to marked drifts of the drain local electrical field and to derating of the drain-source breakdown voltage (process defined as SEB, Single-Event Burnout), or even to extremely high transient flows of charge or overvoltage pulses through active dielectric layers, with consequent permanent dielectric rupture (process defined as SEGR, Single-Event Gate Rupture).        
The above mechanisms are accompanied by an equally harmful degradation (at least in part cumulative) of gate dielectric on the active channel, caused by a drain overcurrent occurring in a transient way due to the interaction between a heavy ion and the active area of the device in the OFF state. In time intervals of a few nanoseconds, an anomalous and intense current of carriers moves in a surface portion of the drain region towards the gate dielectric, and is in part driven by the electrical field towards the channel of the device.
In this regard, reference is made to FIG. 1, showing a VDMOS device 1, comprising in a known manner: a substrate 2 of semiconductor material; an epitaxial surface layer 3, also of semiconductor material, having the same type of conductivity (for example, of an N type) as the substrate 2 and overlying the same substrate 2; a plurality of cells formed in a surface portion of the epitaxial surface layer 3, each comprising a body well 6 having conductivity opposite to that of the epitaxial surface layer 3 (in the example, of a P type), and a source region 7, set within the body well 6, and having the same type of conductivity as the substrate 2; an insulated gate structure 8, constituted by a dielectric gate region 9, formed above the intercell region comprised between adjacent body wells 6 (a surface portion of which is known as neck region, designated by 10) and partially overlapping the body wells 6 and the source regions 7, and by a gate-electrode region 11, formed on the dielectric gate region 9; as is known, the substrate 2 has the function of drain for the VDMOS device 1.
The interaction between a heavy ion and the active area of the device generates a flow of electrons (designated by e) directed towards the substrate 2, and a corresponding flow of holes (designated by p) directed towards the conduction channel of the device (designated by 12 and defined by the portion of the body wells 6 set directly underneath the insulated gate structure 8, and delimited by the junction between the source region 7 and the body well 6 on one side, and by the junction between the body well 6 and the neck region 10, on the other). As highlighted in the detail of FIG. 2 (where field lines are represented with dashed lines), the surface geometry in the active area has a considerable influence in defining the intensity of the electrical-field transverse component Et (i.e., the component directed orthogonally to the surface of the epitaxial surface layer 3). This component, together with the electrical-field longitudinal component El, determines the direction of the resultant electrical field {right arrow over (E)}, which is directed as a whole towards the gate dielectric on the conduction channel 12. A current I directed towards the dielectric gate region 9, or also injected into it, is thus originated, which can entail a progressive charging of the dielectric. This phenomenon can be increased by the effect of current amplification due to the interaction between the charge generated by ionization by the ion and the electrical drain field, and also by triggering of surface conduction of the parasitic bipolar transistor formed by the source region 7, the body region 6, and the drain region (epitaxial surface layer 3).
Typically, technological choices for reducing the incidence of SEGR or charge injection in the dielectric gate region 9 involve the planar geometry of the active area or the thickness of the dielectric gate region 9. In particular, a uniform increase in the thickness of this region (typically constituted of silicon oxide) has proven effective in reducing the probability of SEGR both in the neck region 10 and in the channel region. In fact, the increase in thickness leads to a considerable reduction in the electrical-field transverse component Et, and thus in the injection/trapping of charge in the dielectric. At the same time, however, it has been found that thickening of the gate dielectric leads to a deterioration of the resistance to TID mechanism. Frequently, it is difficult to reach a compromise with TID tolerance, in particular in scaled devices, which typically must guarantee a low ON-resistance (Rdson).